ALPIDE: the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

The upgrade of the ALICE vertex detector, the Inner Tracking System (ITS), is scheduled to be installed during the next long shutdown period (2019-2020) of the CERN Large Hadron Collider (LHC) . The current ITS will be replaced by seven concentric layers of Monolithic Active Pixel Sensors (MAPS) with total active surface of ∼10 m2, thus making ALICE the first LHC experiment implementing MAPS detector technology on a large scale. The ALPIDE chip, based on TowerJazz 180 nm CMOS Imaging Process, is being developed for this purpose. A particular process feature, the deep p-well, is exploited so the full CMOS logic can be implemented over the active sensor area without impinging on the deposited charge collection. ALPIDE is implemented on silicon wafers with a high resistivity epitaxial layer. A single chip measures 15 mm by 30 mm and contains half a million pixels distributed in 512 rows and 1024 columns. In-pixel circuitry features amplification, shaping, discrimination and multi-event buffering. The readout is hit driven i.e. only addresses of hit pixels are sent to the periphery. The upgrade of the ITS presents two different sets of requirements for sensors of the inner and of the outer layers due to the significantly different track density, radiation level and active detector surface. The ALPIDE chip fulfils the stringent requirements in both cases. The detection efficiency is higher than 99%, fake-hit probability is orders of magnitude lower than the required 10−6 and spatial resolution within the required 5 μm. This performance is to be maintained even after a total ionising does (TID) of 2.7 Mrad and a non-ionising energy loss (NIEL) fluence of 1.7 × 1013 1 MeV neq/cm2, which is above what is expected during the detector lifetime. Readout rate of 100 kHz is provided and the power density of ALPIDE is less than 40 mW/cm2. This contribution will provide a summary of the ALPIDE features and main test results.


Introduction
ALICE (A Large Ion Collider Experiment) experiment was designed to address the physics of strongly interacting nuclear matter, and in particular to study the properties of the Quark-Gluon Plasma, using proton-proton, proton-nucleus and nucleus-nucleus collisions at the CERN LHC. The ALICE apparatus is made of several sub-detectors, among which the closest to the colliding region is the Inner Tracking System (ITS), whose upgrade, scheduled for installation during the LHC Long Shutdown 2 in 2019-2020, is necessary to improve the ability to detect heavy-flavour hadrons and low-mass dileptons emitted after the collision. The aim of the upgrade is to improve the impact parameter resolution and the tracking efficiency at low p T while reducing the material budget of the inner layers from 1.14 X 0 down to 0.3 X 0 . The present ITS event readout rate is limited to 1 kHz and the goal of the upgrade is to be able to record Pb-Pb collisions at 100 kHz.
The new ITS will consist of seven layers [1], three in the so-called "Inner Barrel" and four in the "Outer Barrel" (figure 1). All the layers will be populated by MAPS (Monolithic Active Pixel Sensors) [1] with pitch a of about 30 × 30 µm 2 . The forseen reduction of the beam pipe diameter will also allow to install the first layer closer to the interaction point, thus reducing the distance from the current 39 mm to 23 mm. The total sensitive area will cover ∼10 m 2 and will contain about 12.5 × 10 −9 pixels. the pixels will feature binary readout.
The requirements for the sensors to be implemented for the Inner and Outer Barrel are listed in table 1. However, since the same sensor is planned to be used for all the layers, it will have to respect the most stringent requirements of the two cases. In the following the main features of ALPIDE (ALICE PIxel DEtector) design is discussed and the results obtained with the latest full-scale prototype pALPIDE-3 is shown.

Technology
Pixel sensors for the ITS upgrade are based on TowerJazz 180 nm CMOS imaging process [2]. It features the possibilty to implant an n-well on top of a deep p-well (as shown in figure 2) [3] and thus separate all n-wells, except collecting diodes, from the active volume i.e. the epitaxial layer. Therefore, it is possible to implement PMOS transistors inside the pixels, without deteriorating the charge collection efficiency. Finally, this allows for a more complex in-pixel circuitry so ALPIDE is not limited to the traditional rolling shutter readout. All the prototypes, as well as the final ALPIDE chip, are produced on wafers with a high resistivity (>1 kΩ cm) p-type epitaxial layer on a p-type substrate. Sensors with different epitaxial layer thicknesses, ranging from 18 to 40 µm, were produced and tested. The TowerJazz process allows the application of a negative bias to the substrate [4]. Such bias further depletes the high resistivity epitaxial layer (charge collection volume) and increases the strength of the electrical field. Consequently, the charge is collected faster and the fraction of charge collected by the seed pixels is increased, and also the detector capacitance is reduced, therefore signal to noise ratio is improved [5].

Design
The deep p-well feature is fully exploited in the ALPIDE design; each pixel contains an amplifier, a discriminator and a multi-event buffer. Pixels are organised in double-columns (figure 2) each one having 1024 pixels. There are 512 double-columns in an ALPIDE chip thus forming a matrix of 512 rows and 1024 columns. The central part of each double-column is occupied by priority encoding circuits which propagate the addresses of hit pixels to the periphery [6]. There is no clock distributed over the matrix and the pixels which are not hit do not cause activity in the readout circuitry. In general, the entire design is oriented towards very low power consumption; the power consumption of a pixel is about 40 nW, while the power density measured with the latest full-scale prototype is lower than 40 mW/cm 2 .

Principle of operation of the in-pixel circuitry
Simplified layout of in-pixel circuitry i.e. input stage, analogue front-end (amplifier/shaper and discriminator) and digital logic (event buffering and masking), are shown in figure 3. The input stage consists of a collection diode, a continous reset of the input node and a pulse injection capacitance (C inj ) which is used to inject test charges into the analogue front-end. When the charge is collected from the epitaxial layer, there is a fast potential drop at the input node of the amplifing circuit (figure 4a). The reset mechanism then slowly restores the potential to its nominal value. In ALPIDE prototypes two different reset mechanisms, PMOS and diode, were tested and the latter is implemented in the final chip.  The potential drop at the amplifier input node is shaped to a signal with a duration up to 10 µs and peaking time of 1-2 µs (figure 4b). The peaking time and pulse length are chosen such to optimise the power consumption while maintaining the required physics performance. There are several parameters, adjustable via on-chip 8-bit digital-to-analogue converters (DAC), that allow fine tuning of signal shaping and gain. The largest impact on the height and width of the signal is obtained by adjusting the parameter I THR . Increasing its value decreases the amplitude of the signal and the result is equivalent to increasing the discriminator threshold [4]. As long as the amplitude of the signal exceeds the threshold, the discriminator output stays asserted. If the strobe signal, given by the trigger (common to all pixels), is asserted at the same time (figure 4c), the discriminator output state is stored in a state register. Each pixel contains three state registers which therefore act as a multi-event buffer. A latch in the in-pixel digital logic allows to mask the malfunctioning or noisy pixels individually.

Test-beam measurements
The ALPIDE design has been validated in an extensive test-beam campaign by measuring the detection efficiency, the fake-hit rate, the spatial resolution and the radiation hardness of the chip. The campaign was carried out using telescopes made entirely of ALPIDE prototypes at test-beam facilities at CERN, DESY (Germany), LNF (Italy), Pohang (South Korea) and SLRI (Thailand). The results presented in these proceedings are based on the latest full-scale prototype, pALPIDE-3.

pALPIDE-3
In the pALPIDE-3 matrix there are 1024 columns and 512 rows of pixels with pitch of 29.24 × 26.88 µm 2 . Moreover, there are eight pixel flavours which differ in collection diode geometries and/or reset mechanisms. The sensors were produced on wafers with epitaxial layer thickness of 18, 25 and 30 µm. Since the best performing combination of pixel flavour and epitaxial layer thickness has already been selected, only the corresponding results are presented in the following.
The results obtained from the previous full-scale prototypes implied that the main source of fake-hits is the "random telegraph noise" (RTN) originating on the input transistor of the analogue front-end. It is expected that by increasing the transistor size, the effect of the RTN is reduced [3]. Therefore the pALPIDE-3 was produced in two versions featuring different size of the input transistor; pALPIDE-3a features 0.22/0.18 µm (W/L) transistor (as the previous prototypes), while pALPIDE-3b 0.92/0.18 µm (W/L) transistor.

Results
All the presented measurements were carried out using sensors with 25 µm thick epitaxial layer, applying a substrate bias of -6 V and with the 0.015% of the noisiest pixels masked. Figure 5 shows the measured detection efficiency and fake-hit rate of pALPIDE-3a and pALPIDE-3b as a function of the analogue front-end parameter I THR (see section 2.3). Both versions satisfy the ITS upgrade requirements (see table 1) with regard to both the detection efficiency and the fake-hit rate. However the difference in the fake-hit rate is evident; as expected from the larger input transistor, pALPIDE-3b exhibits orders of magnitude lower fake-hit rate and therefore this version is selected for the final ALPIDE design. The impact of irradiating pALPIDE-3b with protons and neutrons on detection efficiency and fake-hit rate is shown in figure 6. The NIEL fluence of 1.7 × 10 13 1 MeV n eq cm −2 has no effect on fake-hit rate while the detection efficiency is reduced. Nevertheless, it is still possible to operate the sensor with efficiency higher than 99% for a wide range of threshold settings. The effect of 349 krad ionising radiation dose is consistent with an effective discriminator threshold value shift.  Figure 6. Detection efficiency and fake-hit rate as a function of I THR ; comparison of pALPIDE-3b performance before and after ionising and non-ionising radiation.
The spatial resolution and the cluster size, before and after irradiation are shown in figure 7. It can be observed that even after receiving the full non-ionising radiation dose expected during the detector lifetime in ALICE, including a safety factor of ten, the detector can be operated with a spatial resolution smaller than 5 µm. The effect of the ionising radiation is in accordance with previously described effective threshold change of the front-end circuit.

Conclusion
ALPIDE is the state of the art Monolithic Active Pixel Sensor to be installed in the new ALICE Inner Tracking System. Its design features asynchronous and sparse readout, and very low power consumption. The performance of the last ALPIDE prototype meets all requirements for the ITS upgrade, including radiation tolerance at least up to the total dose foreseen during the exploitation life time of the detector. Final ALPIDE design has been submitted for production in May 2016 and the validation has started after the delivery in August. The large scale production is scheduled to start by the end of the year.