Reconfigurable PCI Express cards for low-latency data transport in HEP experiments

Ammendola, R. and Biagioni, A. and Cretaro, P. and Frezza, O. and Lamanna, G. (2017) Reconfigurable PCI Express cards for low-latency data transport in HEP experiments. Il nuovo cimento C, 40 (1). pp. 1-5. ISSN 1826-9885

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State-of-the-art technology supports the High Energy Physics community in addressing the problem of managing an overwhelming amount of experimental data. From the point of view of communication between the detectors’ readout system and computing nodes, the critical issues are the following: latency, moving data in a deterministic and low amount of time; bandwidth, guaranteeing the maximum capability of the link and communication protocol adopted; endpoint consolidation, tight aggregation of channels on a single board. This contribution describes the status and performances of the NaNet project, whose goal is the design of a family of FPGA-based PCIe network interface cards. The efforts of the team are focused on implementing a low-latency, real-time data transport mechanism between the board network multi-channel system and CPU and GPU accelerators memories on the host. Several opportunities concerning technical solutions and scientific applications have been explored: NaNet-1 with a single GbE I/O interface, and NaNet-10, offering four 10GbE ports, for activities related to the GPU-based real-time trigger of NA62 experiment at CERN; NaNet3, with four 2.5Gbit optical channels, developed for the KM3NeT-ITALIA underwater neutrino telescope.

Item Type: Article
Subjects: 500 Scienze naturali e Matematica > 530 Fisica
Depositing User: Marina Spanti
Date Deposited: 16 Nov 2020 21:05
Last Modified: 16 Nov 2020 21:05

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