Monteil, E. (2018) A new generation pixel readout ASIC in 65 nm CMOS for HL-LHC experiments. Il nuovo cimento C, 41 (1-2). pp. 1-2. ISSN 1826-9885
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Abstract
A prototype of a readout ASIC in CMOS 65 nm for a pixel detector at high luminosity LHC is described. The chip has been designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue very-front-end designs, one synchronous and one asynchronous, have been implemented. Internal 10-bit DACs are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture which maintains high efficiency (above 99.5%) at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 μs has been developed. The chip has been designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 Collaboration on 65 nm CMOS. Test results of the prototype are described.
| Item Type: | Article |
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| Subjects: | 500 Scienze naturali e Matematica > 530 Fisica |
| Depositing User: | Marina Spanti |
| Date Deposited: | 17 Nov 2020 14:44 |
| Last Modified: | 17 Nov 2020 14:44 |
| URI: | http://eprints.bice.rm.cnr.it/id/eprint/20164 |
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